1. Field of the Invention
This invention relates to a mathematical operation processing apparatus and, more particularly, to a mathematical operation processing apparatus wherein a plurality of computing units individually perform a mathematical operation in synchronism with each other. The present invention relates also to a processing method for such a mathematical operation and a program for causing a computer to execute the processing method.
2. Description of the Related Art
In processor architectures in recent years, it has been proposed frequently to shorten the machine cycle and increase the number of instructions to be executed per one machine cycle to achieve an improvement of the effective performance. As one of such processor architectures, a VLIW (Very Long Instruction Word) system is known. In the VLIW system, a plurality of mathematical operations and so forth are designated in one instruction and executed at the same time.
Generally, when a processor executes a mathematical operation, a state of the mathematical operation is outputted as a condition code together with a result of the mathematical operation. Based on the condition code, for example, coincidence, a mathematical relationship or the like of numerical values can be detected.
According to a processor architecture by the VLIW system in the past, a condition code generated by some of a plurality of instruction processing sections is selected, and a conditional branching instruction or some other conditional instruction is executed based on the selected condition code. The processor architecture of the type described is disclosed, for example, in Japanese Patent Laid-Open No. Hei 9-91141 (FIG. 1).